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| White Electronic Designs 1GB - 2x64Mx72 DDR SDRAM UNBUFFERED FEATURES Double-data rate architecture DDR200, DDR266, DDR333 and DDR400 * JEDEC design specifications BI-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Dual Rank Power supply: * VCC = VCCQ = +2.5V 0.20V (100, 133, 166MHz) * VCC = VCCQ = +2.6V 0.10V (200MHz) JEDEC Standard 184 pin DIMM package * PCB height: 30.48 (1.20") NOTE: Consult factory for availability of: * RoHS compliant products * Vendor source control options * Industrial temperature option W3EG72128S-D3 -JD3 ADVANCED* DESCRIPTION the W3EG72128S is a 2x64Mx72 Double data Rate SDRAM memory module based on 512Mb DDR SDRAM components. The module consists of eighteen 64Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate. Synchronous design allows precisse cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. OPERATING FREQUENCIES DDR400 @CL=3 Clock Speed CL-tRCD-tRP 200MHz 3-3-3 DDR333 @CL=2.5 166MHz 2.5-3-3 DDR266 @CL=2 133MHz 2-2-2 DDR266 @CL=2.5 133MHz 2.5-3-3 DDR200 @CL=2 100MHz 2-2-2 May 2005 Rev. 3 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs PIN CONFIGURATION PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL 1 VREF 47 DQS8 93 VSS 139 VSS 2 DQ0 48 A0 94 DQ4 140 DQM8 3 VSS 49 CB2 95 DQ5 141 A10 96 VCCQ 142 CB6 4 DQ1 50 VSS 5 DQS0 51 CB3 97 DQM0 143 VCCQ 6 DQ2 52 BA1 98 DQ6 144 CB7 7 VCC 53 DQ32 99 DQ7 145 VSS 8 DQ3 54 VCCQ 100 VSS 146 DQ36 9 NC 55 DQ33 101 NC 147 DQ37 10 NC 56 DQS4 102 NC 148 VCC 11 VSS 57 DQ34 103 NC 149 DQM4 12 DQ8 58 VSS 104 VCCQ 150 DQ38 13 DQ9 59 BA0 105 DQ12 151 DQ39 14 DQS1 60 DQ35 106 DQ13 152 VSS 15 VCCQ 61 DQ40 107 DQM1 153 DQ44 16 CK1 62 VCCQ 108 VCC 154 RAS# 17 CK1# 63 WE# 109 DQ14 155 DQ45 18 VSS 64 DQ41 110 DQ15 156 VCCQ 19 DQ10 65 CAS# 111 CKE1 157 CS0# 20 DQ11 66 VSS 112 VCCQ 158 CS1# 21 CKE0 67 DQS5 113 NC 159 DQM5 22 VCCQ 68 DQ42 114 DQ20 160 VSS 23 DQ16 69 DQ43 115 A12 161 DQ46 116 VSS 162 DQ47 24 DQ17 70 VCC 25 DQS2 71 NC 117 DQ21 163 NC 26 VSS 72 DQ48 118 A11 164 VCCQ 27 A9 73 DQ49 119 DQM2 165 DQ52 120 VCC 166 DQ53 28 DQ18 74 VSS 29 A7 75 CK2# 121 DQ22 167 NC 30 VCCQ 76 CK2 122 A8 168 VCC 31 DQ19 77 VCCQ 123 DQ23 169 DQM6 32 A5 78 DQS6 124 VSS 170 DQ54 33 DQ24 79 DQ50 125 A6 171 DQ55 34 VSS 80 DQ51 126 DQ28 172 VCCQ 35 DQ25 81 VSS 127 DQ29 173 NC 36 DQS3 82 VCCID 128 VCCQ 174 DQ60 37 A4 83 DQ56 129 DQM3 175 DQ61 38 VCC 84 DQ57 130 A3 176 VSS 39 DQ26 85 VCC 131 DQ30 177 DQM7 40 DQ27 86 DQS7 132 VSS 178 DQ62 41 A2 87 DQ58 133 DQ31 179 DQ63 42 VSS 88 DQ59 134 CB4 180 VCCQ 43 A1 89 VSS 135 CB5 181 SA0 44 CB0 90 NC 136 VCCQ 182 SA1 45 CB1 91 SDA 137 CK0 183 SA2 46 VCC 92 SCL 138 CK0# 184 VCCSPD A0-A12 BA0-BA1 DQ0-DQ63 CB0-CB7 DQS0-DQS7 CK0, CK1, CK2 CK0#, CK1#, CK2# CKE0, CKE1 CS0#, CS1# RAS# CAS# WE# DQM0-DQM7 VCC VCCQ VSS VREF VCCSPD SDA SCL SA0-SA2 VCCID NC W3EG72128S-D3 -JD3 ADVANCED PIN NAMES Address Input (Multiplexed) Bank Select Address Data Input/Output Check bits Data Strobe Input/Output Clock Input Clock Input Clock Enable input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Data-In Mask Power Supply Power Supply for DQS Ground Power Supply for Reference Serial EEPROM Power Supply Serial data I/O Serial clock Address in EEPROM VCC Indentification Flag No Connect May 2005 Rev. 3 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs FUNCTIONAL BLOCK DIAGRAM CS1# CS0# DQS0 DQM0 DQS4 DQM4 W3EG72128S-D3 -JD3 ADVANCED DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQM1 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQM5 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQM2 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DQM6 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQM3 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQM7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DQM8 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS Serial PD SCL WP A0 SA0 A1 SA1 A2 SA2 SDA BA0-BA1 A0-A12 RAS# CAS# CKE1 CKE0 WE# BA0-BA1: DDR SDRAMs Clock Input SDRAMs 6 SDRAMs 6 SDRAMs 6 SDRAMs A0-A12: DDR SDRAMs CK0/CK0# RAS#: DDR SDRAMs CAS#: DDR SDRAMs CKE: DDR SDRAMs CKE: DDR SDRAMs W E # : DDR SDRAMs CK1/CK1# CK2/CK2# VCCSPD VCC / VCCQ SPD DDR SDRAM V REF DDR SDRAM DDR SDRAM VSS NOTE: All resistor values are 22 ohms unless otherwise specified May 2005 Rev. 3 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current Note: W3EG72128S-D3 -JD3 ADVANCED Symbol VIN, VOUT VCC, VCCQ TSTG PD IOS Value -0.5 to 3.6 -1.0 to 3.6 -55 to +150 18 50 Units V V C W mA Permanent device damage may occur if `ABSOLUTE MAXIMUM RATINGS' are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC CHARACTERISTICS 0C TA 70C, VCC = 2.5V 0.2V Symbol VCC VCCQ VREF VTT VIH VIL VOH VOL Parameter Supply Voltage Supply Voltage Reference Voltage Termination Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Min 2.3 2.3 1.15 1.15 VREF + 0.15 -0.3 VTT + 0.76 -- Max 2.7 2.7 1.35 1.35 VCCQ + 0.3 VREF -0.15 -- VTT-0.76 Unit V V V V V V V V CAPACITANCE TA = 25C. f = 1MHz, VCC = 2.5V 0.2V Parameter Input Capacitance (A0-A12) Input Capacitance (RAS#,CAS#,WE#) Input Capacitance (CKE0, CKE1) Input Capacitance (CK0#, CK0) Input Capacitance (CS0#, CS1#) Input Capacitance (DQM0-DQM8) Input Capacitance (BA0-BA1) Data input/output capacitance (DQ0-DQ63)(DQS) Data input/output capacitance (CB0-CB7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT COUT Max 59 59 32 59 32 13 59 13 13 Unit pF pF pF pF pF pF pF pF pF May 2005 Rev. 3 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs IDD SPECIFICATIONS AND TEST CONDITIONS VCCQ = 2.5V 0.2V, VCC = 2.5V 0.2V; DDR400: VCC = VCCQ = 2.6V 0.1V Includes DDR SDRAM component only DDR400@ CL=3 Max DDR333@ CL=2.5 Max DDR266@ CL=2 Max W3EG72128S-D3 -JD3 ADVANCED Parameter Operating Current Symbol Conditions IDD0 One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. One device bank; Active-ReadPrecharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low) CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. One device bank active; PowerDown mode; tCK (MIN); CKE=(low) CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA. Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. tRC = tRC (MIN) CKE 0.2V Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands. DDR266@ CL=2.5 Max DDR200@ CL=2 Max Units mA 2475 2070 2070 2070 2070 Operating Current IDD1 mA 2745 2340 2340 2340 2340 Precharge PowerDown Standby Current Idle Standby Current IDD2P IDD2F 90 90 90 90 90 rnA mA 990 810 810 810 810 Active Power-Down Standby Current Active Standby Current IDD3P IDD3N 810 630 630 630 630 mA mA 1080 900 900 900 900 Operating Current IDD4R mA 2790 2385 2385 2385 2385 Operating Current IDD4W rnA 2835 2475 2475 2475 2475 Auto Refresh Current Self Refresh Current Operating Current IDD5 IDD6 IDD7A 4185 90 3510 90 3510 90 3510 90 3510 90 mA mA mA 5130 4545 4500 4500 4500 May 2005 Rev. 3 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A IDD1 : OPERATING CURRENT : ONE BANK 1. 2. 3. Typical Case : VCC=2.5V, T=25C Worst Case : VCC=2.7V, T=10C Only one bank is accessed with tRC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. IOUT = 0mA Timing Patterns : * DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRCD=2*tCK, tRAS=5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRCD=10*tCK, tRAS=7*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR400 (200MHz, CL=3) : tCK=5ns, BL=4, tRCD=15*tCK, tRAS=7*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst * W3EG72128S-D3 -JD3 ADVANCED IDD7A : OPERATING CURRENT : FOUR BANKS 1. 2. 3. Typical Case : VCC=2.5V, T=25C Worst Case : VCC=2.7V, T=10C Four banks are being interleaved with tRC (min), Burst Mode, Address and Control inputs on NOP edge are not changing. Iout=0mA Timing Patterns : * DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 repeat the same timing with random address changing; 100% of data changing at every burst DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2, BL=4, tRRD=2*tCK, tRCD=2*tCK Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR400 (200MHz, CL=3) : tCK=5ns, BL=4, tRRD=10*tCK, tRCD=15*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst 4. 4. * * * * * * * Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP A (0-3) = Activate Bank 0-3 R (0-3) = Read Bank 0-3 May 2005 Rev. 3 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs W3EG72128S-D3 -JD3 ADVANCED DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS DDR400: VCC = VCCQ = +2.6V 0.1V; DDR333, 266, 200: VCC = VCCQ = +2.5V 0.2V AC Characteristics Parameter Access window of DQs from CK, CK# CK high-level width CK low-level width Clock cycle time CL=3 CL=2.5 CL=2 DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK, CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK, CK# Data-out low-impedance window from CK, CK# Address and control input hold time (fast slew rate) Address and control input set-up time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) Address and control input pulse width (for each input) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period Symbol tAC tCH tCL tCK (3) tCK (2.5) tCK (2) tDH tDS tDIPW tDQSCK tDQSH tDQSL tDQSQ tDQSS tDSS tDSH tHP tHZ tLZ tIHf tISf tIHs tISs tIPW tMRD tQH tQHS tRAS tRAP tRC tRFC 40 15 55 70 -0.70 0.60 0.60 0.60 0.60 2.2 10 tHP-tQHS 0.55 70,000 42 15 60 72 0.72 0.2 0.2 tCH, tCL +0.70 -0.70 0.75 0.75 0.80 0.80 2.2 12 tHP-tQHS 0.55 70,000 40 15 60 75 Min -0.70 0.45 0.45 5 6 7.5 0.45 0.45 1.75 -0.60 0.35 0.35 0.40 1.28 0.75 0.2 0.2 tCH, tCL +0.70 -0.75 0.90 0.90 1 1 2.2 15 tHP-tQHS 0.75 120,000 45 20 65 75 +0.60 403 Max +0.70 0.55 0.55 7.5 13 13 Min -0.70 0.45 0.45 6 6 7.5 0.45 0.45 1.75 -0.60 +0.60 0.35 0.35 0.45 1.25 0.75 0.2 0.2 tCH, tCL +0.75 -0.75 0.90 0.90 1 1 2.2 15 tHP-tQHS 0.75 120,000 335 Max +0.70 0.55 0.55 13 13 13 262/265 Min -0.75 0.45 0.45 7.5 7.5 7.5 0.5 0.5 1.75 -0.75 0.35 0.35 0.5 1.25 0.75 0.2 0.2 tCH, tCL +0.75 +0.75 Max +0.75 0.55 0.55 13 13 13 Min -0.75 0.45 0.45 7.5 7.5 10 0.5 0.5 1.75 -0.75 0.35 0.35 0.5 1.25 +0.75 202 Max +0.75 0.55 0.55 13 13 13 Units ns tCK tCK ns ns ns ns ns ns ns tCK tCK ns tCK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 21 15 13,14 18 8,19 8,20 6 6 6 6 13,14 16 16 22 22 22 14,17 14,17 17 Notes May 2005 Rev. 3 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs W3EG72128S-D3 -JD3 ADVANCED DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (continued) DDR400: VCC = VCCQ = +2.6V 0.1V; DDR333, 266, 200: VCC = VCCQ = +2.5V 0.2V AC Characteristics Parameter ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window REFRESH to REFRESH command interval Average periodic refresh interval Terminating voltage delay to VCC Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command Symbol tRCD tRP tRPRE tRPST tRRD tWPRE tWPRES tWPST tWR tWTR NA tREFC tREFI tVTD tXSNR tXSRD 0 70 200 Min 15 15 0.9 0.4 10 0.25 0 0.4 15 2 tQH-tDQSQ 70.3 7.8 0 75 200 0.6 1.1 0.6 403 Max Min 15 15 0.9 0.4 12 0.25 0 0.4 15 1 tQH-tDQSQ 70.3 7.8 0 75 200 0.6 1.1 0.6 335 Max 262/265 Min 15 15 0.9 0.4 15 0.25 0 0.4 15 1 tQH-tDQSQ 70.3 7.8 0 75 200 0.6 1.1 0.6 Max Min 20 20 0.9 0.4 15 0.25 0 0.4 15 1 tQH-tDQSQ 70.3 7.8 0.6 1.1 0.6 202 Max Units ns ns tCK tCK ns tCK ns tCK ns tCK ns s s ns ns tCK 13 12 12 10,11 9 Notes May 2005 Rev. 3 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Notes 1. 2. All voltages referenced to VSS Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at normal reference / supply voltage levels, but the related specifications and device operations are guaranteed for the full voltage range specified. Outputs are measured with equivalent load: 12. 11. W3EG72128S-D3 -JD3 ADVANCED It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be high during this time, depending on tDQSS. The refresh period is 64ms. This equates to an average refresh rate of 7.8125s. However, an AUTO REFRESH command must be asserted at least once every 70.3s; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. The valid data window is derived by achieving other specifications - tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycled variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. Referenced to each output group: x8 = DQS with DQ0-DQ7. READs and WRITEs with auto precharge are not allowed to be issued until tRAS (MIN) can be satisfied prior to the internal precharge command being issued. JEDEC specifies CK and CK# input slew rate must be > 1V/ns (2V/ns differentially). DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns, functionality is uncertain. tHP min is the lesser of tCL min and tCH min actually applied to the device CK and CK# inputs, collectively during bank active. tHZ (MAX) will prevail over the tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + PRE (MAX) condition. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps earlier. CKE must be active (High) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tRFC has been satisfied. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles (before READ commands). 3. VTT TT 50 Reference Point 30pF Output (VOUT (VOUT) 13. 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). The AC and DC input level specifications are defined in the SSTL_ 2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [high] level). For slew rates less than 1V/ns and greater than or equal to 0.5V/ ns. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. For 403 and 335, slew rates must be greater than or equal to 0.5V/ns. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE 0.3 x VCCQ is recognized as LOW. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) and begins driving (LZ). The intent of the "Don't Care" state after completion of the postamble is the DQS-driven signal should either be HIGH, LOW, or high-Z, and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions HIGH (above VIHDC (MIN) then it must not transition LOW (below VIHDC) prior to tDQSH (MIN). This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 14. 15. 5. 16. 17. 6. 18. 19. 7. 8. 20. 21. 9. 22. 10. May 2005 Rev. 3 9 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs ORDERING INFORMATION FOR JD3 Part Number W3EG72128S403JD3 W3EG72128S335JD3 W3EG72128S262JD3 W3EG72128S265JD3 W3EG72128S202JD3 Speed 200MHz/400Mb/s 166MHz/333Mb/s 133MHz/266Mb/s 133MHz/266Mb/s 100MHz/200Mb/s CAS Latency 3 2.5 2 2.5 2 tRCD 3 3 2 3 2 W3EG72128S-D3 -JD3 ADVANCED tRP 3 3 2 3 2 Height* 30.48 (1.20") 30.48 (1.20") 30.48 (1.20") 30.48 (1.20") 30.48 (1.20") NOTES: * Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option PACKAGE DIMENSIONS FOR JD3 133.48 (5.255" MAX.) 131.34 (5.171") 128.95 (5.077") 3.99 (0.157 (2x)) 30.48 (1.20) MAX 3.99 (0.157) (MIN) 2.54 (0.100) 17.78 (0.700) 10.01 (0.394) 6.35 (0.250) 64.77 (2.550) 1.27 (0.050 TYP.) 6.35 (0.250) 1.78 (0.070) 49.53 (1.950) 2.31 (0.091) (2x) 3.00 (0.118) (4x) 1.27 0.10 (0.050 0.004) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) May 2005 Rev. 3 10 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs ORDERING INFORMATION FOR D3 Part Number W3EG72128S403D3 W3EG72128S335D3 W3EG72128S262D3 W3EG72128S265D3 W3EG72128S202D3 Speed 200MHz/400Mb/s 166MHz/333Mb/s 133MHz/266Mb/s 133MHz/266Mb/s 100MHz/200Mb/s CAS Latency 3 2.5 2 2.5 2 tRCD 3 3 2 3 2 W3EG72128S-D3 -JD3 ADVANCED tRP 3 3 2 3 2 Height* 30.48 (1.20") 30.48 (1.20") 30.48 (1.20") 30.48 (1.20") 30.48 (1.20") NOTES: * Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option PACKAGE DIMENSIONS FOR D3 133.48 (5.255" MAX.) 131.34 (5.171") 128.95 (5.077") 3.99 (0.157 (2x)) 30.48 (1.20) MAX 3.99 (0.157) (MIN) 2.54 (0.100) 17.78 (0.700) 10.01 (0.394) 6.35 (0.250) 64.77 (2.550) 1.27 (0.050 TYP.) 6.35 (0.250) 1.78 (0.070) 49.53 (1.950) 2.31 (0.091) (2x) 3.00 (0.118) (4x) 1.27 0.10 (0.050 0.004) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) May 2005 Rev. 3 11 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Document Title 1GB - 2x64Mx72 DDR SDRAM UNBUFFERED W3EG72128S-D3 -JD3 ADVANCED Revision History Rev # Rev A Rev B Rev C Rev 0 History Created Datasheet Corrected Mechanical Drawing Added 333MHz speed 0.1 Added 400MHz speed 0.2 Updated AC specs Release Date 3-6-02 5-22-02 2-3-02 10-4-04 Status Advanced Advanced Advanced Advanced Rev 1 1.1 Updated IDD specs 1.2 Updated CAP specs 11-04 Advanced Rev 2 2.1 Added lead-free notes 12-04 Advanced Rev 3 3.1 Added JEDEC Standard (JD3) Package Option 3.2 D3 Not Recommended For New Designs. 5-05 Advanced May 2005 Rev. 3 12 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com |
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